`include "../../src/ShiftLeft_1.v"
`timescale 1ps/1ps

module Add_4Test;
    reg[63:0] in;
    output wire[63:0] out;

    initial
    begin
        #10 in = 64'b0001;
        #10 in = 64'b0010;
        #10 $stop;
    end


    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end

    ShiftLeft_1 U0(in, out);

endmodule